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## Please, don't experiment with monetary policyby Scott Sumner Friday February 16th, 2018 at 11:19 AM

1 Comment

I am seeing an increasing number of pundits calling for policymakers to experiment with the economy. The basic idea seems to be to have (demand-side) policy run hot; to see just how much growth potential is out there. This was a bad idea in the 1960s, and seems like an equally bad idea today. Here's Karl Smith:

Whether by design or default, the nation has found itself in the midst of a momentous economic experiment. A combination of tax cuts and spending increases are creating an economic stimulus as large as the one that was enacted by a Democratic Congress in 2009. That one was a response to the financial crisis, though, and many economists fear that stimulating today's recovering economy would be useless or worse.

Not so fast. There are strong reasons to doubt this claim. I believe that the U.S. economy has significant room to grow. Yet even if I am correct, the burgeoning boom could be cut short by overly aggressive monetary policy.

The Fed is supposed to balance the aims of maximum employment and stable prices. Today, that dual mandate implies that the central bank should be hesitant about raising interest rates, as tax cuts and potential increases in spending on infrastructure and the military work their way through the economy and increase overall demand.

In my view it would be a mistake to experiment with monetary policy by not raising rates. At its best, monetary policy can provide a stable nominal backdrop for the real economy to thrive. What it cannot do is create sustainable growth when the monetary backdrop is already stable.

1. RGDP growth has averaged 1.43% over the past 10 years. During that period, the unemployment rate has fallen from 5.0% to 4.1%. From this we might infer that the recent trend rate of growth is probably below 1.43%. On the other hand, the financial crisis might have depressed growth, even after unemployment recovered.

2. CPI inflation has averaged 1.6% over the past 10 years. PCE inflation has averaged 1.45% over the past 10 years. From this we can infer that PCE inflation is now running about 0.15% below CPI inflation.

3. TIPS spreads are at about 2.1% for 5 and 10-year maturities. These reflect market expectations of CPI inflation, and imply something close to 1.95% inflation for the PCE (which is the index that the Fed targets at 2.0%.)

4. The consensus private sector forecast of inflation over the next few years in 1.9% for 2018, and 2.0% for subsequent years.

5. The unemployment rate of 4.1% is slightly below the Fed's estimate of the natural rate, and forecast to decline further next year.

To summarize, the economy is close to achieving the Fed's dual mandate of 2.0% PCE inflation and high employment, and is expected to continue to roughly achieve this mandate over the next few years. So what kind of expected future monetary policy has brought about these rosy forecasts? Right now, the financial markets are forecasting a number of rate hikes over the next few years. That means that contrary to the claim of Smith, the current condition of the economy does not imply that the Fed should be hesitant about raising interest rates, indeed just the opposite. Not doing so could be destabilizing.

Now it's quite possible that I'm too pessimistic about the long run growth potential of the US economy (which I now estimate at 1.5%). But that doesn't matter. The Fed does not and should not target RGDP. As long as the Fed hits its dual mandate, the growth rate of the economy will depend on the supply-side potential of the US economy. Monetary policy is not going to restrain real growth unless the Fed fails to hit its dual mandate (as in 2008-09, when inflation plunged and unemployment soared.) As long as inflation is near 2% and unemployment is below 5%, then the growth rate of the economy will not be held back by monetary policy. I can't emphasize enough that monetary policy is not some sort of magic wand that can "solve problems". The very best we can expect from monetary policy is to refrain from causing problems. I frequently disagree with the Austrian school on monetary policy, but this is one area where I agree. Monetary policy cannot solve problems; it can merely refrain from causing them. It is not something we should be experimenting with.

I was pleased to see the cover of the new Economist:

But my heart sank when I read the article:

In some ways today's experiment looks more like the boom of the late 1990s (see Free Exchange). Alan Greenspan, then chairman of the Federal Reserve, kept monetary policy loose enough to push unemployment down to 3.8% by April 2000. Mr Greenspan had correctly anticipated that computerisation would increase the economy's productive capacity and let some of the pressure out of the expansion. Inflation stayed comfortably below 2% even as wages soared. The boom eventually came to an end because a bubble in technology stocks popped--and, perhaps, because Mr Greenspan was less alert to recessionary signals than he had been to evidence of technological change.
Isn't a more likely explanation that the Fed let the economy run too hot in 2000, and that this contributed to the subsequent recession? Business cycles are not just caused by contractionary mistakes (as some Keynesian accounts seem to imply) and they aren't just caused by expansionary mistakes, (as some Austrian accounts seem to imply.) They are caused by unstable monetary policy---more expansionary that average in some years, and less expansionary that average in other years.

Let's keep monetary policy exactly average, every single year. That's the policy that will best allow us to see the potential growth rate of the economy.

PS. I'm not trying to tar all Keynesians and Austrians, just giving a sense of the tendencies I see on each side---the more extreme views of the hard core in each group. In contrast, Milton Friedman didn't always get it right, but he did have a balanced set of criticisms of monetary policy---too easy at times, and too tight at other times.

HT: Caroline Baum

stefanetal
1 day ago
I've not kept track of the learning in macroeconomics literature, but a while back that literature had a surprising lack of good papers. And almost no papers worked out experimental learning strategies for the monetary authority. I should probably peak and see what's out there now. But it was one of the impressive lacunae of macro (and one that people didn't complain about much or were even aware of, while one might argue that it is central to what's going on).
Northern Virginia

## Sergeant Spoof's Time Has Passedby Matt Levine Wednesday January 31st, 2018 at 11:33 AM

1 Comment
Also insider trading, securities fraud, merger appraisal, crypto and Dimon 2024.
stefanetal
17 days ago
I’ve never understood why spoofing is bad beyond tying up server bandwidth and slowing down other orders (and that might not even be bad either! — and its easy to solve by charging a tiny bit for cancellations). All outcomes are part of sophisticated entities playing a game, so analyzing this isn’t easy, but in equilibrium making price less responsive to perceived order flow isn’t the worst thing (but it depends). Seems like side show.
Northern Virginia
duerig
17 days ago
I've long believed that what we really need is a per-transaction stock trading tax. One cent per transaction + 10 cent cancellation fee. There is no good reason to provide liquidity at the millisecond or even second timescale which is the only social utility of high speed trading. What do you think?

## Hunting for new physics in a black hole’s shadowby Aaron Tohuvavohu Wednesday January 24th, 2018 at 9:51 PM

1 Comment

Authors: Steven B. Giddings & Dimitrios Psaltis

First Author’s Institution: University of California, Santa Barbara

Status: Submitted to Phys Rev D, open access on the arXiv.

For 5 days in April of 2017, 8 radio telescopes on 4 continents all pointed in concert at Sagittarius A*, the supermassive black hole at the center of our galaxy. During this observing campaign these 8 telescopes effectively became one Earth-sized radio telescope, the Event Horizon Telescope (EHT). Using hydrogen maser atomic clocks to track the difference in the arrival times of the radio signal at the various telescopes, the far-flung array can emulate a single telescope with an effective diameter equal to that of our planet, a technique called very long baseline interferometry (VLBI).

Figure 1. The Event Horizon Telescope network. The nodes are the individual radio telescopes that make up the network, and the connections are the baselines between them. (Image Credit: ESO)

The goal of the EHT project is to directly image the immediate environs of a black hole, a region that has been inaccessible with light thus far. The unprecedented angular resolution achieved by the EHT is approximately 50 micro arcseconds (approximately the resolution needed to see an apple on the surface of the moon from your house), not coincidentally the same angular size on the sky as the event horizon of Sgr A* and that of the super-massive black hole at the heart of the elliptical galaxy M87. While M87 is much farther away than the Galactic Center, the mass of its central black hole is $\sim 6.5 \times 10 ^ 9$ solar masses, about 1500 times more massive than Sgr A*. Since the size of the event horizon scales linearly with the mass of the black hole, the angular sizes subtended on the sky by the event horizons of Sgr A* and M87’s black hole end up being comparable.

Alongside the recent successes of gravitational wave astronomy, the EHT is another way to probe the  ‘strong-field’ gravitational regime and provide long-awaited answers to questions about general relativity. Specifically, the EHT uses mm-wavelength radio astronomy to trace the extremely hot gas that is believed to inhabit the area directly outside the event horizon of the black hole. General relativity predicts that a silhouette, or ‘shadow’, will be seen imprinted onto the image of the hot gas, the distinct signature of the black hole’s event horizon (See Fig. 2). Today’s paper looks at ways to test general relativity, alternative theories of gravity, and the quantum structure of space-time by studying the size and shape of this shadow.

Figure 2. At left: A simulated image of Sgr A* showing the hot accretion flow. The light coming from the hot gas is lensed by the strong gravity and forms a ring that encircles the distinctive shadow of the black hole. The ring is brighter on the approaching side and dimmer on the receding side due to Doppler effects. At right: The expected performance of the EHT array during its 2017 observing run. [arxiv:1409.4690]

In general relativity, the event horizon of a Schwarzschild (non-spinning) black hole should be perfectly circular and its radius should scale with the black hole’s mass as $2MG/c^2$, where $M$ is mass of the black hole, $G$ is the gravitational constant, and $c$ is the speed of light. In the more astrophysically realistic case where a black hole has spin, described by the Kerr metric, the event horizon will still look very circular unless the spin is exceptionally large and the inclination angle is high (line-of-sight is near the axis of rotation). However, in beyond-GR theories the event horizon can be asymmetric, and the size can vary.

In this paper the authors study the observable effects of what they call ‘soft quantum modifications’ on the black hole shadow. What this really means is that instead of the space-time being smooth and well described by general relativity, it takes on a jittery quantized behavior at certain length scales. A bumpy space-time may sound strange, but is not completely uncalled for, and such an approach is well motivated by a variety of outstanding issues (see Bites on: hairy black holes, quantized gravity, and the black hole information paradox).

Figure 3. Possible shapes of the event horizon that can result from small perturbations to the black hole’s structure. Left and right show different phases of the same perturbation mode. One should imagine the black hole pulsating back-and-forth between these shapes. The blue circle shows the shape of the event horizon in the regular non-spinning general relativistic (Schwarzschild) case. (Figure 5 in the paper)

The authors allow small changes (perturbations) to the structure of the black hole space-time (the metric), of the sort that might be allowed in a reasonable theory of quantum gravity. They then calculate what the shape of the horizon looks like under these perturbations (Fig. 3), and the effect that this has on the path that light takes around the black hole.  The authors find that introducing these small changes to the structure of the black hole space-time can have significant and time-dependent (not to mention beautiful) effects on the shape of the shadow that is cast onto the image of the bright gas (see Fig. 4). If these effects exist, they could in some cases be easily distinguished from their cousins, the more staid classical black hole shadows. However, they observe that in their model the dynamical variations in the shadow have a characteristic time-scale that is proportional to $\frac{1}{M},$ with $M$ the mass of the black-hole. In other words, the less massive the black hole, the more time that will pass between noticeable variations in the black hole’s shadow.  This period ends up being just too long for observations of Sgr A*. That is, while the observations of Sgr A* taken in April may be able to resolve strange, non-circular shapes (if there are quantum gravitational perturbations at all!), we will not be able to see the shape of the horizon changing. However, because M87 is so much more massive, its characteristic pulsation period is short enough to capture in a typical EHT observation.

Figure 4. A simulated image of the effect of the quantum perturbations on the light coming off the hot gas near the black hole. (Figure 9 in the paper)

This paper is a worthwhile and fun exploration of possible effects that a quantum structure of space-time could have on black hole shadows, but there are some limitations. The ‘soft quantum modifications’ were made only for non-spinning (Schwarzschild) black holes. Extending these methods to the spinning case is not trivial, but there are reasons to believe that the results will be at least qualitatively similar. Most importantly however, those searching for hints of a theory beyond General Relativity in black hole shadows now know what to look for.

While the EHT observations were performed in April, the results are not out yet. VLBI techniques require significant data processing, and the team only just received the data taken by the South Pole Telescope (the node that provides the longest baseline) via the sneakernet. There are no flights out of the South Pole during the austral winter and too much data to send via the internet (even if it wasn’t the strictly bandwidth limited TDRSS network that provides the South Pole station’s connection!). While it remains to be seen, it’s possible that the first direct image of the event horizon of a black hole is sitting in the data, just waiting to be pieced together, and with it possible clues about the quantum structure of space-time.

stefanetal
24 days ago
Another cool, just like imaging stellar surfaces, that wasn't around or forseen when you were a kid: event horizon imaging. But I'd not expect new fundamental physics out of it just yet (that's how these things have been going). New 'applied' astrophysics is good to though.
Northern Virginia

## This is the Surface of a Giant Star, 350 Times Larger Than the Sunby Matt Williams Wednesday January 24th, 2018 at 9:46 PM

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When it comes to looking beyond our Solar System, astronomers are often forced to theorize about what they don’t know based on what they do. In short, they have to rely on what we have learned studying the Sun and the planets from our own Solar System in order to make educated guesses about how other star systems and their respective bodies formed and evolved.

For example, astronomers have learned much from our Sun about how convection plays a major role in the life of stars. Until now, they have not been able to conduct detailed studies of the surfaces of other stars because of their distances and obscuring factors. However, in a historic first, an international team of scientists recently created the first detailed images of the surface of a red giant star located roughly 530 light-years away.

The study recently appeared in the scientific journal Nature under the title “Large Granulation cells on the surface of the giant star Π¹ Gruis“. The study was led by Claudia Paladini of the Université libre de Bruxelles and included members from the European Southern Observatory, the Université de Nice Sophia-Antipolis, Georgia State University, the Université Grenoble Alpes, Uppsala University, the University of Vienna, and the University of Exeter.

The surface of the red giant star Π¹ Gruis from PIONIER on the VLT. Credit: ESO

For the sake of their study, the team used the Precision Integrated-Optics Near-infrared Imaging ExpeRiment (PIONIER) instrument on the ESO’s Very Large Telescope Interferometer (VLTI) to observe the star known as Π¹ Gruis. Located 530 light-years from Earth in the constellation of Grus (The Crane), Π1 Gruis is a cool red giant. While it is the same mass as our Sun, it is 350 times larger and several thousand times as bright.

For decades, astronomers have sought to learn more about the convection properties and evolution of stars by studying red giants. These are what become of main sequence stars once they have exhausted their hydrogen fuel and expand to becomes hundreds of times their normal diameter. Unfortunately, studying the convection properties of most supergiant stars has been challenging because their surfaces are frequently obscured by dust.

After obtaining interferometric data on Π1 Gruis in September of 2014, the team then relied on image reconstruction software and algorithms to compose images of the star’s surface. These allowed the team to determine the convection patterns of the star by picking out its “granules”, the large grainy spots on the surface that indicate the top of a convective cell.

This was the first time that such images have been created, and represent a major breakthrough when it comes to our understanding of how stars age and evolve. As Dr. Fabien Baron, an assistant professor at Georgia State University and a co-author on the study, explained:

“This is the first time that we have such a giant star that is unambiguously imaged with that level of details. The reason is there’s a limit to the details we can see based on the size of the telescope used for the observations. For this paper, we used an interferometer. The light from several telescopes is combined to overcome the limit of each telescope, thus achieving a resolution equivalent to that of a much larger telescope.”

Artist’s impression of the Earth scorched by our Sun as it enters its Red Giant Branch phase. Credit: Wikimedia Commons/Fsgregs

This study is especially significant because Π1 Gruis in the last major phase of life and resembles what our Sun will look like when it is at the end of its lifespan. In other words, when our Sun exhausts its hydrogen fuel in roughly five billion years, it will expand significantly to become a red giant star. At this point, it will be large enough to encompass Mercury, Venus, and maybe even Earth.

As a result, studying this star will give scientists insight into the future activity, characteristics and appearance of our Sun. For instance, our Sun has about two million convective cells that typically measure 2,000 km (1243 mi) in diameter. Based on their study, the team estimates that the surface of Π1 Gruis has a complex convective pattern, with granules measuring about 1.2 x 10^8 km (62,137,119 mi) horizontally or 27 percent of the diameter of the star.

This is consistent with what astronomers have predicted, which was that giant and supergiant stars should only have a few large convective cells because of their low surface gravity. As Baron indicated:

“These images are important because the size and number of granules on the surface actually fit very well with models that predict what we should be seeing. That tells us that our models of stars are not far from reality. We’re probably on the right track to understand these kinds of stars.”

An illustration of the structure of the Sun and a red giant star, showing their convective zones. These are the granular zones in the outer layers of the stars. Credit: ESO

The detailed map also indicated differences in surface temperature, which were apparent from the different colors on the star’s surface. This are also consistent with what we know about stars, where temperature variations are indicative of processes that are taking place inside. As temperatures rise and fall, the hotter, more fluid areas become brighter (appearing white) while the cooler, denser areas become darker (red).

Looking ahead, Paladini and her team want to create even more detailed images of the surface of giant stars. The main aim of this is to be able to follow the evolution of these granules continuously, rather than merely getting snapshots of different points in time.

From these and similar studies, we are not only likely to learn more about the formation and evolution of different types of stars in our Universe; we’re also sure to get a better understanding of what our Solar System is in for.

Further Reading: Georgia State University, ESO, Nature

The post This is the Surface of a Giant Star, 350 Times Larger Than the Sun appeared first on Universe Today.

stefanetal
24 days ago
Stuff you learned as a kids isn't true anymore. Like 'nobody has resolved a stellar image.' Star being large helps too. This isn't the first one either (but it sounds like the best use of doing so yet, with good results).
Northern Virginia

## Reading privileged memory with a side-channelby Ben (noreply@blogger.com) Wednesday January 3rd, 2018 at 9:34 PM

1 Comment and 3 Shares
Posted by Jann Horn, Project Zero

We have discovered that CPU data cache timing can be abused to efficiently leak information out of mis-speculated execution, leading to (at worst) arbitrary virtual memory read vulnerabilities across local security boundaries in various contexts.

Variants of this issue are known to affect many modern processors, including certain processors by Intel, AMD and ARM. For a few Intel and AMD CPU models, we have exploits that work against real software. We reported this issue to Intel, AMD and ARM on 2017-06-01 [1].

So far, there are three known variants of the issue:

• Variant 1: bounds check bypass (CVE-2017-5753)
• Variant 2: branch target injection (CVE-2017-5715)
• Variant 3: rogue data cache load (CVE-2017-5754)

Before the issues described here were publicly disclosed, Daniel Gruss, Moritz Lipp, Yuval Yarom, Paul Kocher, Daniel Genkin, Michael Schwarz, Mike Hamburg, Stefan Mangard, Thomas Prescher and Werner Haas also reported them; their [writeups/blogposts/paper drafts] are at:

During the course of our research, we developed the following proofs of concept (PoCs):

1. A PoC that demonstrates the basic principles behind variant 1 in userspace on the tested Intel Haswell Xeon CPU, the AMD FX CPU, the AMD PRO CPU and an ARM Cortex A57 [2]. This PoC only tests for the ability to read data inside mis-speculated execution within the same process, without crossing any privilege boundaries.
2. A PoC for variant 1 that, when running with normal user privileges under a modern Linux kernel with a distro-standard config, can perform arbitrary reads in a 4GiB range [3] in kernel virtual memory on the Intel Haswell Xeon CPU. If the kernel's BPF JIT is enabled (non-default configuration), it also works on the AMD PRO CPU. On the Intel Haswell Xeon CPU, kernel virtual memory can be read at a rate of around 2000 bytes per second after around 4 seconds of startup time. [4]
3. A PoC for variant 2 that, when running with root privileges inside a KVM guest created using virt-manager on the Intel Haswell Xeon CPU, with a specific (now outdated) version of Debian's distro kernel [5] running on the host, can read host kernel memory at a rate of around 1500 bytes/second, with room for optimization. Before the attack can be performed, some initialization has to be performed that takes roughly between 10 and 30 minutes for a machine with 64GiB of RAM; the needed time should scale roughly linearly with the amount of host RAM. (If 2MB hugepages are available to the guest, the initialization should be much faster, but that hasn't been tested.)
4. A PoC for variant 3 that, when running with normal user privileges, can read kernel memory on the Intel Haswell Xeon CPU under some precondition. We believe that this precondition is that the targeted kernel memory is present in the L1D cache.

For interesting resources around this topic, look down into the "Literature" section.

A warning regarding explanations about processor internals in this blogpost: This blogpost contains a lot of speculation about hardware internals based on observed behavior, which might not necessarily correspond to what processors are actually doing.

We have some ideas on possible mitigations and provided some of those ideas to the processor vendors; however, we believe that the processor vendors are in a much better position than we are to design and evaluate mitigations, and we expect them to be the source of authoritative guidance.

The PoC code and the writeups that we sent to the CPU vendors will be made available at a later date.

# Tested Processors

• Intel(R) Xeon(R) CPU E5-1650 v3 @ 3.50GHz (called "Intel Haswell Xeon CPU" in the rest of this document)
• AMD FX(tm)-8320 Eight-Core Processor (called "AMD FX CPU" in the rest of this document)
• AMD PRO A8-9600 R7, 10 COMPUTE CORES 4C+6G (called "AMD PRO CPU" in the rest of this document)
• An ARM Cortex A57 core of a Google Nexus 5x phone [6] (called "ARM Cortex A57" in the rest of this document)

# Glossary

retire: An instruction retires when its results, e.g. register writes and memory writes, are committed and made visible to the rest of the system. Instructions can be executed out of order, but must always retire in order.

logical processor core: A logical processor core is what the operating system sees as a processor core. With hyperthreading enabled, the number of logical cores is a multiple of the number of physical cores.

cached/uncached data: In this blogpost, "uncached" data is data that is only present in main memory, not in any of the cache levels of the CPU. Loading uncached data will typically take over 100 cycles of CPU time.

speculative execution: A processor can execute past a branch without knowing whether it will be taken or where its target is, therefore executing instructions before it is known whether they should be executed. If this speculation turns out to have been incorrect, the CPU can discard the resulting state without architectural effects and continue execution on the correct execution path. Instructions do not retire before it is known that they are on the correct execution path.

mis-speculation window: The time window during which the CPU speculatively executes the wrong code and has not yet detected that mis-speculation has occurred.

# Variant 1: Bounds check bypass

This section explains the common theory behind all three variants and the theory behind our PoC for variant 1 that, when running in userspace under a Debian distro kernel, can perform arbitrary reads in a 4GiB region of kernel memory in at least the following configurations:

• Intel Haswell Xeon CPU, eBPF JIT is off (default state)
• Intel Haswell Xeon CPU, eBPF JIT is on (non-default state)
• AMD PRO CPU, eBPF JIT is on (non-default state)

The state of the eBPF JIT can be toggled using the net.core.bpf_jit_enable sysctl.

## Theoretical explanation

The Intel Optimization Reference Manual says the following regarding Sandy Bridge (and later microarchitectural revisions) in section 2.3.2.3 ("Branch Prediction"):

Branch prediction predicts the branch target and enables the
processor to begin executing instructions long before the branch
true execution path is known.

In section 2.3.5.2 ("L1 DCache"):

[...]
• Be carried out speculatively, before preceding branches are resolved.
• Take cache misses out of order and in an overlapped manner.

Intel's Software Developer's Manual [7] states in Volume 3A, section 11.7 ("Implicit Caching (Pentium 4, Intel Xeon, and P6 family processors"):

Implicit caching occurs when a memory element is made potentially cacheable, although the element may never have been accessed in the normal von Neumann sequence. Implicit caching occurs on the P6 and more recent processor families due to aggressive prefetching, branch prediction, and TLB miss handling. Implicit caching is an extension of the behavior of existing Intel386, Intel486, and Pentium processor systems, since software running on these processor families also has not been able to deterministically predict the behavior of instruction prefetch.
Consider the code sample below. If arr1->length is uncached, the processor can speculatively load data from arr1->data[untrusted_offset_from_caller]. This is an out-of-bounds read. That should not matter because the processor will effectively roll back the execution state when the branch has executed; none of the speculatively executed instructions will retire (e.g. cause registers etc. to be affected).

struct array {
unsigned long length;
unsigned char data[];
};
struct array *arr1 = ...;
unsigned long untrusted_offset_from_caller = ...;
if (untrusted_offset_from_caller < arr1->length) {
unsigned char value = arr1->data[untrusted_offset_from_caller];
...
}
However, in the following code sample, there's an issue. If arr1->length, arr2->data[0x200] and arr2->data[0x300] are not cached, but all other accessed data is, and the branch conditions are predicted as true, the processor can do the following speculatively before arr1->length has been loaded and the execution is re-steered:

• start a load from a data-dependent offset in arr2->data, loading the corresponding cache line into the L1 cache

struct array {
unsigned long length;
unsigned char data[];
};
struct array *arr1 = ...; /* small array */
struct array *arr2 = ...; /* array of size 0x400 */
/* >0x400 (OUT OF BOUNDS!) */
unsigned long untrusted_offset_from_caller = ...;
if (untrusted_offset_from_caller < arr1->length) {
unsigned char value = arr1->data[untrusted_offset_from_caller];
unsigned long index2 = ((value&1)*0x100)+0x200;
if (index2 < arr2->length) {
unsigned char value2 = arr2->data[index2];
}
}

After the execution has been returned to the non-speculative path because the processor has noticed that untrusted_offset_from_caller is bigger than arr1->length, the cache line containing arr2->data[index2] stays in the L1 cache. By measuring the time required to load arr2->data[0x200] and arr2->data[0x300], an attacker can then determine whether the value of index2 during speculative execution was 0x200 or 0x300 - which discloses whether arr1->data[untrusted_offset_from_caller]&1 is 0 or 1.

To be able to actually use this behavior for an attack, an attacker needs to be able to cause the execution of such a vulnerable code pattern in the targeted context with an out-of-bounds index. For this, the vulnerable code pattern must either be present in existing code, or there must be an interpreter or JIT engine that can be used to generate the vulnerable code pattern. So far, we have not actually identified any existing, exploitable instances of the vulnerable code pattern; the PoC for leaking kernel memory using variant 1 uses the eBPF interpreter or the eBPF JIT engine, which are built into the kernel and accessible to normal users.

A minor variant of this could be to instead use an out-of-bounds read to a function pointer to gain control of execution in the mis-speculated path. We did not investigate this variant further.

## Attacking the kernel

This section describes in more detail how variant 1 can be used to leak Linux kernel memory using the eBPF bytecode interpreter and JIT engine. While there are many interesting potential targets for variant 1 attacks, we chose to attack the Linux in-kernel eBPF JIT/interpreter because it provides more control to the attacker than most other JITs.

The Linux kernel supports eBPF since version 3.18. Unprivileged userspace code can supply bytecode to the kernel that is verified by the kernel and then:

• either interpreted by an in-kernel bytecode interpreter
• or translated to native machine code that also runs in kernel context using a JIT engine (which translates individual bytecode instructions without performing any further optimizations)

Execution of the bytecode can be triggered by attaching the eBPF bytecode to a socket as a filter and then sending data through the other end of the socket.

Whether the JIT engine is enabled depends on a run-time configuration setting - but at least on the tested Intel processor, the attack works independent of that setting.

Unlike classic BPF, eBPF has data types like data arrays and function pointer arrays into which eBPF bytecode can index. Therefore, it is possible to create the code pattern described above in the kernel using eBPF bytecode.

eBPF's data arrays are less efficient than its function pointer arrays, so the attack will use the latter where possible.

Both machines on which this was tested have no SMAP, and the PoC relies on that (but it shouldn't be a precondition in principle).

Additionally, at least on the Intel machine on which this was tested, bouncing modified cache lines between cores is slow, apparently because the MESI protocol is used for cache coherence [8]. Changing the reference counter of an eBPF array on one physical CPU core causes the cache line containing the reference counter to be bounced over to that CPU core, making reads of the reference counter on all other CPU cores slow until the changed reference counter has been written back to memory. Because the length and the reference counter of an eBPF array are stored in the same cache line, this also means that changing the reference counter on one physical CPU core causes reads of the eBPF array's length to be slow on other physical CPU cores (intentional false sharing).

The attack uses two eBPF programs. The first one tail-calls through a page-aligned eBPF function pointer array prog_map at a configurable index. In simplified terms, this program is used to determine the address of prog_map by guessing the offset from prog_map to a userspace address and tail-calling through prog_map at the guessed offsets. To cause the branch prediction to predict that the offset is below the length of prog_map, tail calls to an in-bounds index are performed in between. To increase the mis-speculation window, the cache line containing the length of prog_map is bounced to another core. To test whether an offset guess was successful, it can be tested whether the userspace address has been loaded into the cache.

Because such straightforward brute-force guessing of the address would be slow, the following optimization is used: 215 adjacent userspace memory mappings [9], each consisting of 24 pages, are created at the userspace address user_mapping_area, covering a total area of 231 bytes. Each mapping maps the same physical pages, and all mappings are present in the pagetables.

This permits the attack to be carried out in steps of 231 bytes. For each step, after causing an out-of-bounds access through prog_map, only one cache line each from the first 24 pages of user_mapping_area have to be tested for cached memory. Because the L3 cache is physically indexed, any access to a virtual address mapping a physical page will cause all other virtual addresses mapping the same physical page to become cached as well.

When this attack finds a hit—a cached memory location—the upper 33 bits of the kernel address are known (because they can be derived from the address guess at which the hit occurred), and the low 16 bits of the address are also known (from the offset inside user_mapping_area at which the hit was found). The remaining part of the address of user_mapping_area is the middle.

The remaining bits in the middle can be determined by bisecting the remaining address space: Map two physical pages to adjacent ranges of virtual addresses, each virtual address range the size of half of the remaining search space, then determine the remaining address bit-wise.

At this point, a second eBPF program can be used to actually leak data. In pseudocode, this program looks as follows:

uint64_t bitshift_selector = <runtime-configurable>;
uint64_t prog_array_base_offset = <runtime-configurable>;
uint64_t secret_data_offset = <runtime-configurable>;
// index will be bounds-checked by the runtime,
// but the bounds check will be bypassed speculatively
// select a single bit, move it to a specific position, and add the base offset
uint64_t progmap_index = (((secret_data & bitmask) >> bitshift_selector) << 7) + prog_array_base_offset;
bpf_tail_call(prog_map, progmap_index);

This program reads 8-byte-aligned 64-bit values from an eBPF data array "victim_map" at a runtime-configurable offset and bitmasks and bit-shifts the value so that one bit is mapped to one of two values that are 27 bytes apart (sufficient to not land in the same or adjacent cache lines when used as an array index). Finally it adds a 64-bit offset, then uses the resulting value as an offset into prog_map for a tail call.

This program can then be used to leak memory by repeatedly calling the eBPF program with an out-of-bounds offset into victim_map that specifies the data to leak and an out-of-bounds offset into prog_map that causes prog_map + offset to point to a userspace memory area. Misleading the branch prediction and bouncing the cache lines works the same way as for the first eBPF program, except that now, the cache line holding the length of victim_map must also be bounced to another core.

# Variant 2: Branch target injection

This section describes the theory behind our PoC for variant 2 that, when running with root privileges inside a KVM guest created using virt-manager on the Intel Haswell Xeon CPU, with a specific version of Debian's distro kernel running on the host, can read host kernel memory at a rate of around 1500 bytes/second.

## Basics

Prior research (see the Literature section at the end) has shown that it is possible for code in separate security contexts to influence each other's branch prediction. So far, this has only been used to infer information about where code is located (in other words, to create interference from the victim to the attacker); however, the basic hypothesis of this attack variant is that it can also be used to redirect execution of code in the victim context (in other words, to create interference from the attacker to the victim; the other way around).

The basic idea for the attack is to target victim code that contains an indirect branch whose target address is loaded from memory and flush the cache line containing the target address out to main memory. Then, when the CPU reaches the indirect branch, it won't know the true destination of the jump, and it won't be able to calculate the true destination until it has finished loading the cache line back into the CPU, which takes a few hundred cycles. Therefore, there is a time window of typically over 100 cycles in which the CPU will speculatively execute instructions based on branch prediction.

## Haswell branch prediction internals

Some of the internals of the branch prediction implemented by Intel's processors have already been published; however, getting this attack to work properly required significant further experimentation to determine additional details.

This section focuses on the branch prediction internals that were experimentally derived from the Intel Haswell Xeon CPU.

Haswell seems to have multiple branch prediction mechanisms that work very differently:

• A generic branch predictor that can only store one target per source address; used for all kinds of jumps, like absolute jumps, relative jumps and so on.
• A specialized indirect call predictor that can store multiple targets per source address; used for indirect calls.
• (There is also a specialized return predictor, according to Intel's optimization manual, but we haven't analyzed that in detail yet. If this predictor could be used to reliably dump out some of the call stack through which a VM was entered, that would be very interesting.)

### Generic predictor

The generic branch predictor, as documented in prior research, only uses the lower 31 bits of the address of the last byte of the source instruction for its prediction. If, for example, a branch target buffer (BTB) entry exists for a jump from 0x4141.0004.1000 to 0x4141.0004.5123, the generic predictor will also use it to predict a jump from 0x4242.0004.1000. When the higher bits of the source address differ like this, the higher bits of the predicted destination change together with it—in this case, the predicted destination address will be 0x4242.0004.5123—so apparently this predictor doesn't store the full, absolute destination address.

Before the lower 31 bits of the source address are used to look up a BTB entry, they are folded together using XOR. Specifically, the following bits are folded together:

 bit A bit B 0x40.0000 0x2000 0x80.0000 0x4000 0x100.0000 0x8000 0x200.0000 0x1.0000 0x400.0000 0x2.0000 0x800.0000 0x4.0000 0x2000.0000 0x10.0000 0x4000.0000 0x20.0000

In other words, if a source address is XORed with both numbers in a row of this table, the branch predictor will not be able to distinguish the resulting address from the original source address when performing a lookup. For example, the branch predictor is able to distinguish source addresses 0x100.0000 and 0x180.0000, and it can also distinguish source addresses 0x100.0000 and 0x180.8000, but it can't distinguish source addresses 0x100.0000 and 0x140.2000 or source addresses 0x100.0000 and 0x180.4000. In the following, this will be referred to as aliased source addresses.

When an aliased source address is used, the branch predictor will still predict the same target as for the unaliased source address. This indicates that the branch predictor stores a truncated absolute destination address, but that hasn't been verified.

Based on observed maximum forward and backward jump distances for different source addresses, the low 32-bit half of the target address could be stored as an absolute 32-bit value with an additional bit that specifies whether the jump from source to target crosses a 232 boundary; if the jump crosses such a boundary, bit 31 of the source address determines whether the high half of the instruction pointer should increment or decrement.

### Indirect call predictor

The inputs of the BTB lookup for this mechanism seem to be:

• The low 12 bits of the address of the source instruction (we are not sure whether it's the address of the first or the last byte) or a subset of them.
• The branch history buffer state.

If the indirect call predictor can't resolve a branch, it is resolved by the generic predictor instead. Intel's optimization manual hints at this behavior: "Indirect Calls and Jumps. These may either be predicted as having a monotonic target or as having targets that vary in accordance with recent program behavior."

The branch history buffer (BHB) stores information about the last 29 taken branches - basically a fingerprint of recent control flow - and is used to allow better prediction of indirect calls that can have multiple targets.

The update function of the BHB works as follows (in pseudocode; src is the address of the last byte of the source instruction, dst is the destination address):

void bhb_update(uint58_t *bhb_state, unsigned long src, unsigned long dst) {
*bhb_state <<= 2;
*bhb_state ^= (dst & 0x3f);
*bhb_state ^= (src & 0xc0) >> 6;
*bhb_state ^= (src & 0xc00) >> (10 - 2);
*bhb_state ^= (src & 0xc000) >> (14 - 4);
*bhb_state ^= (src & 0x30) << (6 - 4);
*bhb_state ^= (src & 0x300) << (8 - 8);
*bhb_state ^= (src & 0x3000) >> (12 - 10);
*bhb_state ^= (src & 0x30000) >> (16 - 12);
*bhb_state ^= (src & 0xc0000) >> (18 - 14);
}

Some of the bits of the BHB state seem to be folded together further using XOR when used for a BTB access, but the precise folding function hasn't been understood yet.

The BHB is interesting for two reasons. First, knowledge about its approximate behavior is required in order to be able to accurately cause collisions in the indirect call predictor. But it also permits dumping out the BHB state at any repeatable program state at which the attacker can execute code - for example, when attacking a hypervisor, directly after a hypercall. The dumped BHB state can then be used to fingerprint the hypervisor or, if the attacker has access to the hypervisor binary, to determine the low 20 bits of the hypervisor load address (in the case of KVM: the low 20 bits of the load address of kvm-intel.ko).

### Reverse-Engineering Branch Predictor Internals

This subsection describes how we reverse-engineered the internals of the Haswell branch predictor. Some of this is written down from memory, since we didn't keep a detailed record of what we were doing.

We initially attempted to perform BTB injections into the kernel using the generic predictor, using the knowledge from prior research that the generic predictor only looks at the lower half of the source address and that only a partial target address is stored. This kind of worked - however, the injection success rate was very low, below 1%. (This is the method we used in our preliminary PoCs for method 2 against modified hypervisors running on Haswell.)

We decided to write a userspace test case to be able to more easily test branch predictor behavior in different situations.

Based on the assumption that branch predictor state is shared between hyperthreads [10], we wrote a program of which two instances are each pinned to one of the two logical processors running on a specific physical core, where one instance attempts to perform branch injections while the other measures how often branch injections are successful. Both instances were executed with ASLR disabled and had the same code at the same addresses. The injecting process performed indirect calls to a function that accesses a (per-process) test variable; the measuring process performed indirect calls to a function that tests, based on timing, whether the per-process test variable is cached, and then evicts it using CLFLUSH. Both indirect calls were performed through the same callsite. Before each indirect call, the function pointer stored in memory was flushed out to main memory using CLFLUSH to widen the speculation time window. Additionally, because of the reference to "recent program behavior" in Intel's optimization manual, a bunch of conditional branches that are always taken were inserted in front of the indirect call.

In this test, the injection success rate was above 99%, giving us a base setup for future experiments.

We then tried to figure out the details of the prediction scheme. We assumed that the prediction scheme uses a global branch history buffer of some kind.

To determine the duration for which branch information stays in the history buffer, a conditional branch that is only taken in one of the two program instances was inserted in front of the series of always-taken conditional jumps, then the number of always-taken conditional jumps (N) was varied. The result was that for N=25, the processor was able to distinguish the branches (misprediction rate under 1%), but for N=26, it failed to do so (misprediction rate over 99%).
Therefore, the branch history buffer had to be able to store information about at least the last 26 branches.

The code in one of the two program instances was then moved around in memory. This revealed that only the lower 20 bits of the source and target addresses have an influence on the branch history buffer.

Testing with different types of branches in the two program instances revealed that static jumps, taken conditional jumps, calls and returns influence the branch history buffer the same way; non-taken conditional jumps don't influence it; the address of the last byte of the source instruction is the one that counts; IRETQ doesn't influence the history buffer state (which is useful for testing because it permits creating program flow that is invisible to the history buffer).

Moving the last conditional branch before the indirect call around in memory multiple times revealed that the branch history buffer contents can be used to distinguish many different locations of that last conditional branch instruction. This suggests that the history buffer doesn't store a list of small history values; instead, it seems to be a larger buffer in which history data is mixed together.

However, a history buffer needs to "forget" about past branches after a certain number of new branches have been taken in order to be useful for branch prediction. Therefore, when new data is mixed into the history buffer, this can not cause information in bits that are already present in the history buffer to propagate downwards - and given that, upwards combination of information probably wouldn't be very useful either. Given that branch prediction also must be very fast, we concluded that it is likely that the update function of the history buffer left-shifts the old history buffer, then XORs in the new state (see diagram).

If this assumption is correct, then the history buffer contains a lot of information about the most recent branches, but only contains as many bits of information as are shifted per history buffer update about the last branch about which it contains any data. Therefore, we tested whether flipping different bits in the source and target addresses of a jump followed by 32 always-taken jumps with static source and target allows the branch prediction to disambiguate an indirect call. [11]

With 32 static jumps in between, no bit flips seemed to have an influence, so we decreased the number of static jumps until a difference was observable. The result with 28 always-taken jumps in between was that bits 0x1 and 0x2 of the target and bits 0x40 and 0x80 of the source had such an influence; but flipping both 0x1 in the target and 0x40 in the source or 0x2 in the target and 0x80 in the source did not permit disambiguation. This shows that the per-insertion shift of the history buffer is 2 bits and shows which data is stored in the least significant bits of the history buffer. We then repeated this with decreased amounts of fixed jumps after the bit-flipped jump to determine which information is stored in the remaining bits.

## Reading host memory from a KVM guest

### Locating the host kernel

Our PoC locates the host kernel in several steps. The information that is determined and necessary for the next steps of the attack consists of:

• lower 20 bits of the address of kvm-intel.ko

Looking back, this is unnecessarily complicated, but it nicely demonstrates the various techniques an attacker can use. A simpler way would be to first determine the address of vmlinux, then bisect the addresses of kvm.ko and kvm-intel.ko.

In the first step, the address of kvm-intel.ko is leaked. For this purpose, the branch history buffer state after guest entry is dumped out. Then, for every possible value of bits 12..19 of the load address of kvm-intel.ko, the expected lowest 16 bits of the history buffer are computed based on the load address guess and the known offsets of the last 8 branches before guest entry, and the results are compared against the lowest 16 bits of the leaked history buffer state.

The branch history buffer state is leaked in steps of 2 bits by measuring misprediction rates of an indirect call with two targets. One way the indirect call is reached is from a vmcall instruction followed by a series of N branches whose relevant source and target address bits are all zeroes. The second way the indirect call is reached is from a series of controlled branches in userspace that can be used to write arbitrary values into the branch history buffer.
Misprediction rates are measured as in the section "Reverse-Engineering Branch Predictor Internals", using one call target that loads a cache line and another one that checks whether the same cache line has been loaded.

With N=29, mispredictions will occur at a high rate if the controlled branch history buffer value is zero because all history buffer state from the hypercall has been erased. With N=28, mispredictions will occur if the controlled branch history buffer value is one of 0<<(28*2), 1<<(28*2), 2<<(28*2), 3<<(28*2) - by testing all four possibilities, it can be detected which one is right. Then, for decreasing values of N, the four possibilities are {0|1|2|3}<<(28*2) | (history_buffer_for(N+1) >> 2). By repeating this for decreasing values for N, the branch history buffer value for N=0 can be determined.

At this point, the low 20 bits of kvm-intel.ko are known; the next step is to roughly locate kvm.ko.
For this, the generic branch predictor is used, using data inserted into the BTB by an indirect call from kvm.ko to kvm-intel.ko that happens on every hypercall; this means that the source address of the indirect call has to be leaked out of the BTB.

kvm.ko will probably be located somewhere in the range from 0xffffffffc0000000 to 0xffffffffc4000000, with page alignment (0x1000). This means that the first four entries in the table in the section "Generic Predictor" apply; there will be 24-1=15 aliasing addresses for the correct one. But that is also an advantage: It cuts down the search space from 0x4000 to 0x4000/24=1024.

To find the right address for the source or one of its aliasing addresses, code that loads data through a specific register is placed at all possible call targets (the leaked low 20 bits of kvm-intel.ko plus the in-module offset of the call target plus a multiple of 220) and indirect calls are placed at all possible call sources. Then, alternatingly, hypercalls are performed and indirect calls are performed through the different possible non-aliasing call sources, with randomized history buffer state that prevents the specialized prediction from working. After this step, there are 216 remaining possibilities for the load address of kvm.ko.

Next, the load address of vmlinux can be determined in a similar way, using an indirect call from vmlinux to kvm.ko. Luckily, none of the bits which are randomized in the load address of vmlinux  are folded together, so unlike when locating kvm.ko, the result will directly be unique. vmlinux has an alignment of 2MiB and a randomization range of 1GiB, so there are still only 512 possible addresses.
Because (as far as we know) a simple hypercall won't actually cause indirect calls from vmlinux to kvm.ko, we instead use port I/O from the status register of an emulated serial port, which is present in the default configuration of a virtual machine created with virt-manager.

The only remaining piece of information is which one of the 16 aliasing load addresses of kvm.ko is actually correct. Because the source address of an indirect call to kvm.ko is known, this can be solved using bisection: Place code at the various possible targets that, depending on which instance of the code is speculatively executed, loads one of two cache lines, and measure which one of the cache lines gets loaded.

### Identifying cache sets

The PoC assumes that the VM does not have access to hugepages.To discover eviction sets for all L3 cache sets with a specific alignment relative to a 4KiB page boundary, the PoC first allocates 25600 pages of memory. Then, in a loop, it selects random subsets of all remaining unsorted pages such that the expected number of sets for which an eviction set is contained in the subset is 1, reduces each subset down to an eviction set by repeatedly accessing its cache lines and testing whether the cache lines are always cached (in which case they're probably not part of an eviction set) and attempts to use the new eviction set to evict all remaining unsorted cache lines to determine whether they are in the same cache set [12].

### Locating the host-virtual address of a guest page

Because this attack uses a FLUSH+RELOAD approach for leaking data, it needs to know the host-kernel-virtual address of one guest page. Alternative approaches such as PRIME+PROBE should work without that requirement.

The basic idea for this step of the attack is to use a branch target injection attack against the hypervisor to load an attacker-controlled address and test whether that caused the guest-owned page to be loaded. For this, a gadget that simply loads from the memory location specified by R8 can be used - R8-R11 still contain guest-controlled values when the first indirect call after a guest exit is reached on this kernel build.

We expected that an attacker would need to either know which eviction set has to be used at this point or brute-force it simultaneously; however, experimentally, using random eviction sets works, too. Our theory is that the observed behavior is actually the result of L1D and L2 evictions, which might be sufficient to permit a few instructions worth of speculative execution.

The host kernel maps (nearly?) all physical memory in the physmap area, including memory assigned to KVM guests. However, the location of the physmap is randomized (with a 1GiB alignment), in an area of size 128PiB. Therefore, directly bruteforcing the host-virtual address of a guest page would take a long time. It is not necessarily impossible; as a ballpark estimate, it should be possible within a day or so, maybe less, assuming 12000 successful injections per second and 30 guest pages that are tested in parallel; but not as impressive as doing it in a few minutes.

To optimize this, the problem can be split up: First, brute-force the physical address using a gadget that can load from physical addresses, then brute-force the base address of the physmap region. Because the physical address can usually be assumed to be far below 128PiB, it can be brute-forced more efficiently, and brute-forcing the base address of the physmap region afterwards is also easier because then address guesses with 1GiB alignment can be used.

ffffffff810a9def:       4c 89 c0                mov    rax,r8
ffffffff810a9df2:       4d 63 f9                movsxd r15,r9d
ffffffff810a9df5:       4e 8b 04 fd c0 b3 a6    mov    r8,QWORD PTR [r15*8-0x7e594c40]
ffffffff810a9dfc:       81
ffffffff810a9dfd:       4a 8d 3c 00             lea    rdi,[rax+r8*1]
ffffffff810a9e01:       4d 8b a4 00 f8 00 00    mov    r12,QWORD PTR [r8+rax*1+0xf8]
ffffffff810a9e08:       00

This gadget permits loading an 8-byte-aligned value from the area around the kernel text section by setting R9 appropriately, which in particular permits loading page_offset_base, the start address of the physmap. Then, the value that was originally in R8 - the physical address guess minus 0xf8 - is added to the result of the previous load, 0xfa is added to it, and the result is dereferenced.

### Cache set selection

To select the correct L3 eviction set, the attack from the following section is essentially executed with different eviction sets until it works.

### Leaking data

At this point, it would normally be necessary to locate gadgets in the host kernel code that can be used to actually leak data by reading from an attacker-controlled location, shifting and masking the result appropriately and then using the result of that as offset to an attacker-controlled address for a load. But piecing gadgets together and figuring out which ones work in a speculation context seems annoying. So instead, we decided to use the eBPF interpreter, which is built into the host kernel - while there is no legitimate way to invoke it from inside a VM, the presence of the code in the host kernel's text section is sufficient to make it usable for the attack, just like with ordinary ROP gadgets.

The eBPF interpreter entry point has the following function signature:

static unsigned int __bpf_prog_run(void *ctx, const struct bpf_insn *insn)

The second parameter is a pointer to an array of statically pre-verified eBPF instructions to be executed - which means that __bpf_prog_run() will not perform any type checks or bounds checks. The first parameter is simply stored as part of the initial emulated register state, so its value doesn't matter.

The eBPF interpreter provides, among other things:

• multiple emulated 64-bit registers
• 64-bit immediate writes to emulated registers
• bitwise operations (including bit shifts) and arithmetic operations

To call the interpreter entry point, a gadget that gives RSI and RIP control given R8-R11 control and controlled data at a known memory location is necessary. The following gadget provides this functionality:

ffffffff81514edd:       4c 89 ce                mov    rsi,r9
ffffffff81514ee0:       41 ff 90 b0 00 00 00    call   QWORD PTR [r8+0xb0]

Now, by pointing R8 and R9 at the mapping of a guest-owned page in the physmap, it is possible to speculatively execute arbitrary unvalidated eBPF bytecode in the host kernel. Then, relatively straightforward bytecode can be used to leak data into the cache.

# Variant 3: Rogue data cache load

In summary, an attack using this variant of the issue attempts to read kernel memory from userspace without misdirecting the control flow of kernel code. This works by using the code pattern that was used for the previous variants, but in userspace. The underlying idea is that the permission check for accessing an address might not be on the critical path for reading data from memory to a register, where the permission check could have significant performance impact. Instead, the memory read could make the result of the read available to following instructions immediately and only perform the permission check asynchronously, setting a flag in the reorder buffer that causes an exception to be raised if the permission check fails.

We do have a few additions to make to Anders Fogh's blogpost:

"Imagine the following instruction executed in usermode
It will cause an interrupt when retired, [...]"

It is also possible to already execute that instruction behind a high-latency mispredicted branch to avoid taking a page fault. This might also widen the speculation window by increasing the delay between the read from a kernel address and delivery of the associated exception.

"First, I call a syscall that touches this memory. Second, I use the prefetcht0 instruction to improve my odds of having the address loaded in L1."

When we used prefetch instructions after doing a syscall, the attack stopped working for us, and we have no clue why. Perhaps the CPU somehow stores whether access was denied on the last access and prevents the attack from working if that is the case?

"Fortunately I did not get a slow read suggesting that Intel null’s the result when the access is not allowed."

That (read from kernel address returns all-zeroes) seems to happen for memory that is not sufficiently cached but for which pagetable entries are present, at least after repeated read attempts. For unmapped memory, the kernel address read does not return a result at all.

# Ideas for further research

We believe that our research provides many remaining research topics that we have not yet investigated, and we encourage other public researchers to look into these.
This section contains an even higher amount of speculation than the rest of this blogpost - it contains untested ideas that might well be useless.

## Leaking without data cache timing

It would be interesting to explore whether there are microarchitectural attacks other than measuring data cache timing that can be used for exfiltrating data out of speculative execution.

## Other microarchitectures

Our research was relatively Haswell-centric so far. It would be interesting to see details e.g. on how the branch prediction of other modern processors works and how well it can be attacked.

## Other JIT engines

We developed a successful variant 1 attack against the JIT engine built into the Linux kernel. It would be interesting to see whether attacks against more advanced JIT engines with less control over the system are also practical - in particular, JavaScript engines.

## More efficient scanning for host-virtual addresses and cache sets

In variant 2, while scanning for the host-virtual address of a guest-owned page, it might make sense to attempt to determine its L3 cache set first. This could be done by performing L3 evictions using an eviction pattern through the physmap, then testing whether the eviction affected the guest-owned page.

The same might work for cache sets - use an L1D+L2 eviction set to evict the function pointer in the host kernel context, use a gadget in the kernel to evict an L3 set using physical addresses, then use that to identify which cache sets guest lines belong to until a guest-owned eviction set has been constructed.

## Dumping the complete BTB state

Given that the generic BTB seems to only be able to distinguish 231-8 or fewer source addresses, it seems feasible to dump out the complete BTB state generated by e.g. a hypercall in a timeframe around the order of a few hours. (Scan for jump sources, then for every discovered jump source, bisect the jump target.) This could potentially be used to identify the locations of functions in the host kernel even if the host kernel is custom-built.

The source address aliasing would reduce the usefulness somewhat, but because target addresses don't suffer from that, it might be possible to correlate (source,target) pairs from machines with different KASLR offsets and reduce the number of candidate addresses based on KASLR being additive while aliasing is bitwise.

This could then potentially allow an attacker to make guesses about the host kernel version or the compiler used to build it based on jump offsets or distances between functions.

## Variant 2: Leaking with more efficient gadgets

If sufficiently efficient gadgets are used for variant 2, it might not be necessary to evict host kernel function pointers from the L3 cache at all; it might be sufficient to only evict them from L1D and L2.

## Various speedups

In particular the variant 2 PoC is still a bit slow. This is probably partly because:

• It only leaks one bit at a time; leaking more bits at a time should be doable.
• It heavily uses IRETQ for hiding control flow from the processor.

It would be interesting to see what data leak rate can be achieved using variant 2.

## Leaking or injection through the return predictor

If the return predictor also doesn't lose its state on a privilege level change, it might be useful for either locating the host kernel from inside a VM (in which case bisection could be used to very quickly discover the full address of the host kernel) or injecting return targets (in particular if the return address is stored in a cache line that can be flushed out by the attacker and isn't reloaded before the return instruction).

However, we have not performed any experiments with the return predictor that yielded conclusive results so far.

## Leaking data out of the indirect call predictor

We have attempted to leak target information out of the indirect call predictor, but haven't been able to make it work.

# Vendor statements

The following statement were provided to us regarding this issue from the vendors to whom Project Zero disclosed this vulnerability:

## Intel

No current statement provided at this time.

## AMD

No current statement provided at this time.

## ARM

Arm recognises that the speculation functionality of many modern high-performance processors, despite working as intended, can be used in conjunction with the timing of cache operations to leak some information as described in this blog. Correspondingly, Arm has developed software mitigations that we recommend be deployed.

Specific details regarding the affected processors and mitigations can be found at this website: www.arm.com/security-update

Arm has included a detailed technical whitepaper as well as links to information from some of Arm’s architecture partners regarding their specific implementations and mitigations.

# Literature

Note that some of these documents - in particular Intel's documentation - change over time, so quotes from and references to it may not reflect the latest version of Intel's documentation.

• https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf: Intel's optimization manual has many interesting pieces of optimization advice that hint at relevant microarchitectural behavior; for example:
• "Placing data immediately following an indirect branch can cause a performance problem. If the data consists of all zeros, it looks like a long stream of ADDs to memory destinations and this can cause resource conflicts and slow down branch recovery. Also, data immediately following indirect branches may appear as branches to the branch predication [sic] hardware, which can branch off to execute other data pages. This can lead to subsequent self-modifying code problems."
• "Loads can:[...]Be carried out speculatively, before preceding branches are resolved."
• "Software should avoid writing to a code page in the same 1-KByte subpage that is being executed or fetching code in the same 2-KByte subpage of that is being written. In addition, sharing a page containing directly or speculatively executed code with another processor as a data page can trigger an SMC condition that causes the entire pipeline of the machine and the trace cache to be cleared. This is due to the self-modifying code condition."
• "if mapped as WB or WT, there is a potential for speculative processor reads to bring the data into the caches"
• "Failure to map the region as WC may allow the line to be speculatively read into the processor caches (via the wrong path of a mispredicted branch)."
• https://software.intel.com/en-us/articles/intel-sdm: Intel's Software Developer Manuals
• http://www.agner.org/optimize/microarchitecture.pdf: Agner Fog's documentation of reverse-engineered processor behavior and relevant theory was very helpful for this research.
• http://www.cs.binghamton.edu/~dima/micro16.pdf and https://github.com/felixwilhelm/mario_baslr: Prior research by Dmitry Evtyushkin, Dmitry Ponomarev and Nael Abu-Ghazaleh on abusing branch target buffer behavior to leak addresses that we used as a starting point for analyzing the branch prediction of Haswell processors. Felix Wilhelm's research based on this provided the basic idea behind variant 2.
• https://arxiv.org/pdf/1507.06955.pdf: The rowhammer.js research by Daniel Gruss, Clémentine Maurice and Stefan Mangard contains information about L3 cache eviction patterns that we reused in the KVM PoC to evict a function pointer.
• https://xania.org/201602/bpu-part-one: Matt Godbolt blogged about reverse-engineering the structure of the branch predictor on Intel processors.
• https://www.sophia.re/thesis.pdf: Sophia D'Antoine wrote a thesis that shows that opcode scheduling can theoretically be used to transmit data between hyperthreads.
• https://gruss.cc/files/kaiser.pdf: Daniel Gruss, Moritz Lipp, Michael Schwarz, Richard Fellner, Clémentine Maurice, and Stefan Mangard wrote a paper on mitigating microarchitectural issues caused by pagetable sharing between userspace and the kernel.
• https://www.jilp.org/: This journal contains many articles on branch prediction.
• http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/: This blogpost by Henry Wong investigates the L3 cache replacement policy used by Intel's Ivy Bridge architecture.

# References

[1] This initial report did not contain any information about variant 3. We had discussed whether direct reads from kernel memory could work, but thought that it was unlikely. We later tested and reported variant 3 prior to the publication of Anders Fogh's work at https://cyber.wtf/2017/07/28/negative-result-reading-kernel-memory-from-user-mode/.
[2] The precise model names are listed in the section "Tested Processors". The code for reproducing this is in the writeup_files.tar archive in our bugtracker, in the folders userland_test_x86 and userland_test_aarch64.
[3] The attacker-controlled offset used to perform an out-of-bounds access on an array by this PoC is a 32-bit value, limiting the accessible addresses to a 4GiB window in the kernel heap area.
[4] This PoC won't work on CPUs with SMAP support; however, that is not a fundamental limitation.
[5] linux-image-4.9.0-3-amd64 at version 4.9.30-2+deb9u2 (available at http://snapshot.debian.org/archive/debian/20170701T224614Z/pool/main/l/linux/linux-image-4.9.0-3-amd64_4.9.30-2%2Bdeb9u2_amd64.deb, sha256 5f950b26aa7746d75ecb8508cc7dab19b3381c9451ee044cd2edfd6f5efff1f8, signed via Release.gpg, Release, Packages.xz); that was the current distro kernel version when I set up the machine. It is very unlikely that the PoC works with other kernel versions without changes; it contains a number of hardcoded addresses/offsets.
[6] The phone was running an Android build from May 2017.
[9] More than 215 mappings would be more efficient, but the kernel places a hard cap of 216 on the number of VMAs that a process can have.
[10] Intel's optimization manual states that "In the first implementation of HT Technology, the physical execution resources are shared and the architecture state is duplicated for each logical processor", so it would be plausible for predictor state to be shared. While predictor state could be tagged by logical core, that would likely reduce performance for multithreaded processes, so it doesn't seem likely.
[11] In case the history buffer was a bit bigger than we had measured, we added some margin - in particular because we had seen slightly different history buffer lengths in different experiments, and because 26 isn't a very round number.
[12] The basic idea comes from http://palms.ee.princeton.edu/system/files/SP_vfinal.pdf, section IV, although the authors of that paper still used hugepages.

acdha
45 days ago
👏🏼
Washington, DC
stefanetal
45 days ago
This made my day. I'm so happy.
stefanetal
45 days ago
Northern Virginia

## Alabama’s White Voters Abandoned Roy Moore in Large Numbersby Kevin Drum Friday December 15th, 2017 at 5:47 PM

1 Comment

I’m curious about something, but first a caveat: data from exit polls isn’t always perfect. However, more reliable data from the ACS and ANES surveys aren’t available yet for the 2017 vote in Alabama. And that’s not all: exit polls aren’t even available for Alabama every year, since everyone knows who’s going to win there and it hardly seems worth it. Still, exit polls are all we have right now, and we do have exit polls from both the 2008 and 2017 Senate races:

There’s not much change except in one category: a whole lot of white voters who voted for Republican Jeff Sessions in 2008 decided to vote for Democrat Doug Jones in 2017.

Obviously Barack Obama was also on the ballot in 2008, and that makes a difference. At the same time, there doesn’t seem to be anything all that special about either black turnout or the huge share of the vote they gave Jones (98 percent vs. 90 percent for Vivian Davis Figures in 2008). The biggest difference appears to be in the large number of white voters who apparently couldn’t bring themselves to vote for Roy Moore and voted instead for the Democrat (30 percent vs. 11 percent for Figures in 2008).

Am I missing something here?